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Publications


* The materials on this webpage are presented to ensure timely dissemination of scholarly and technical works. Copyright holders include the IEEE, IET and ACM. Available for personal, non-commercial purposes only.

** CLICK HERE FOR MY DYNAMIC LIST OF PUBLICATIONS FROM THE UNIVERSITY REPOSITORY


 

Books

  1. Xuan-Tu Tran. Network-on-Chip (Mạng trên Chip). Vietnam National University Publishing House, 2020, ISBN: 978-604-9947-49-0.
  2. Xuan-Tu Tran (editor). Emerging Aspects in Electronics and Communication Engineering. Vietnam National University Publishing House, 2013, ISBN: 978-604-62-0984-3.

Patents

  1. Patent No. 1-0021424 (1-2017-00868). Quy trình mã hóa liên khung hình hỗ trợ xác định khối ảnh lặp lại, giảm kích thước chuỗi bit sau mã hóa và loại bỏ hiệu ứng do sai số lượng tử cho khối ảnh lặp lại. Authors: Xuan-Tu Tran, Ngoc-Sinh Nguyen, Duy-Hieu Bui.

Journal Papers

  1. Dinh-Lam Tran, Xuan-Tu Tran, Duy-Hieu Bui, Cong-Kha Pham. An Efficient Hardware Implementation of Residual Data Binarization in HEVC CABAC Encoder. Electronics, vol. 9, issue 4, p. 684, April 2020. ISSN 2079-9292 (SCI, IF 1.764, Q1)
  2. Khanh N. Dang, Michael Meyer, Akram Ben Ahmed, Abderazek Ben Abdallah, Xuan-Tu Tran. A non-blocking non-degrading multiple defects link testing method for 3D-Networks-on-Chip. IEEE Access, 8, pp. 59571-59589. ISSN 2169-3536 (SCIE, IF 4.098, Q1)
  3. Khanh N. Dang, Michael Meyer, Akram Ben Ahmed, Abderazek Ben Abdallah, Xuan-Tu Tran. 2D-PPC: A single-correction multiple-detection method for Through-Silicon-Via Faults. REV Journal on Electronics and Communications, 2020. ISSN: 1859-387X.
  4. Xuan-Tu Tran, Ngoc-Sinh Nguyen, Duy-Hieu Bui, Minh-Trien Pham, Kiem-Hung Nguyen, Cong-Kha Pham. Reducing Bitrate and Increasing the Quality of Inter Frame by Avoiding Quantization Error in Stationary Blocks. EAI Transactions on Industrial Networks and Intelligent Systems, vol. 20, issue 22, January 2020. ISSN 2410-0218.
  5. Khanh N. Dang, Akram Ben Ahmed, Ben Abdallah Abderrazak, Xuan-Tu Tran. TSV-OCT: A Scalable Online Multiple-TSV Defects Localization for Real-Time 3-D-IC Systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 3, pp. 672-685, March 2020. ISSN 1063-8210. (SCI, IF 1.946) [Early Access]
  6. Hung K. Nguyen, Xuan-Tu Tran. A novel reconfigurable router for QoS guarantees in real-time NoC-based MPSoCs.  Journal of Systems Architecture, Vol. 100, November 2019. [Early Access] (SCI, IF 1.159)
  7. Dinh-Lam Tran, Viet-Huong Pham, Hung K. Nguyen, Xuan-Tu Tran. A Survey of High-Efficient CABAC Hardware Implementations in HEVC Standard. VNU Journal of Computer Science and Communication Engineering, 35 (2), 2019. pp. 1-21. ISSN 0866-8612.
  8. Nam Khanh Dang, Xuan Tu Tran. An Adaptive and High Coding Rate Soft Error Correction Method in Network-on-Chips. VNU Journal of Computer Science and Communication Engineering, pp. 32-45, Vol. 35, Issue 1, June 2019. ISSN 0866-8612.
  9. Duy Hieu Bui, Diego Puschini, Simone Bacles-Min, Edith Beigne, Xuan Tu Tran. AES Datapath Optimization Strategies for Low-Power low-Energy Multi-security-level Internet-of-Thing Applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 25, Issue 12, December 2017, pp. 3281-3290. ISSN 1063-8210. (SCI, IF 1.946)
  10. Nam Khanh Dang, Akram Ben Ahmed, Xuan Tu Tran, Yuichi Okuyama, Abderazek Ben Abdallah. A Comprehensive Reliability Assessment of Fault-Resilient Network-on-Chip Using Analytical Model. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 25, Issue 11, pp. 3099-3112, August 2017. ISSN 1063-8210. (SCI, IF 1.946)
  11. Hung K. Nguyen, Thanh-Vu Le-Van, Xuan-Tu Tran. A Survey on Reconfigurable System-on-Chips. REV Journal on Electronics and Communications (JEC), 2017, ISSN: 1859-387X. 
  12. Xuan-Tu Tran, Tung Nguyen, Hai-Phong Phan, Duy-Hieu Bui. AXI-NoC: High-Performance Adaptation Unit for ARM Processors in Network-on-Chip Architectures. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E100-A, No.8, pp. 1650-1660, Aug. 2017, ISSN: 1745-1337. [DOI] (SCIE)
  13. Hung K. Nguyen, Xuan-Tu Tran. An Efficient Implementation of Advanced Encryption Standard on the Coarse-grained Reconfigurable Architecture. VNU Journal of Computer Science and Communication Engineering (JCSCE), Vol. 32, No. 2, 2016, ISSN: 0866-8612.
  14. Hai-Phong Phan, Xuan-Tu Tran. Design and Modeling of a Voltage-Frequency Controller for Network-on-Chip Routers base on Fuzzy-Logic. VNU Journal of Computer Science and Communication Engineering (JCSCE), pp. 56-65, Vol. 31, No. 2, 2015, ISSN: 0866-8612. [PDF|PrePrint|URL]
  15. Thanh-Vu Le-Van, Xuan-Tu Tran. High-Level Modeling and Simulation of a Novel Reconfigurable Network-on-Chip Router. REV Journal on Electronics and Communications (JEC), pp. 68-74, Vol. 4, No. 3-4, July-December, 2014, ISSN: 1859 – 387X. [PDF|PrePrint|URL]
  16. Ngoc-Mai Nguyen, Edith Beigne, Duy-Hieu Bui, Nam-Khanh Dang, Suzanne Lesecq, Pascal Vivet, Xuan-Tu Tran. An Overview of H.264 Hardware Encoder Architectures including Low-Power Features. REV Journal on Electronics and Communications (JEC), pp. 8-17, Vol. 4, No. 1-2, January - June, 2014, ISSN: 1859-387X. [PDF|PrePrint|URL]
  17. Xuan-Tu Tran, Van-Huan Tran. An Efficient Architecture of Forward Transforms and Quantization for H.264/AVC Codecs. REV Journal on Electronics and Communications (JEC), pp. 122-129, Vol. 1, No. 2, April-August, 2011, ISSN: 1859-387X. [PDF|PrePrint|URL]
  18. Van-Huan Tran, Xuan-Tu Tran. CoMoSy: a Flexible System-on-Chip Platform for Embedded Applications. Journal of Research, Development, and Application on Information and Communication Theory, pp. 2-11, Vol. E-1, No.4 (8), June 2011, ISSN 1859-3534. [PDF|PrePrint|URL]
  19. Xuan-Tu Tran, Yvain Thonnart, Jean Durupt, Vincent Beroulle, and Chantal Robach. Design-for-Test Approach of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application. IET Journal on Computers and Digital Techniques, Volume 3, Issue 5, pp. 487-500, September 2009, ISSN 1751-8601. (SCIE, IF 0.857) [URL|DOI] - citations
  20. Beigne, E.; Clermidy, F.; Lhermet, H.; Miermont, S.; Thonnart, Y.; Tran, X.; Valentian, A.; Varreau, D.; Vivet, P.; Popon, X.; Lebreton, H. An Asynchronous Power Aware and Adaptive NoC Based Circuit. IEEE Journal of Solid State Circuits (JSSC), Volume 44, Issue 4, pp. 1167-1177, April 2009, ISSN 0018-9200. (SCI, IF 5.173, Q1) [URL|DOI] - citations

 

Conference Papers in reverse chronologic order

  1. Al-Shatari, Mohammed and Azmadi Hussin, Fawnizu and Abd Aziz, Azrina and Witjaksono, Gunawan and Saufy Rohmad, Mohd and Tran, Xuan-Tu (2019) An Efficient Implementation of LED Block Cipher on FPGA. The First International Conference of Intelligent Computing and Engineering (ICOICE), 15-16 December 2019, Yemen.
  2. Nguyen, Ngo Doanh and Bui, Duy Hieu and Tran, Xuan Tu (2019) A Novel Hardware Architecture for Human Detection using HOG-SVM Co-Optimization. In: IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 11-14 November 2019, Bangkok.
  3. Dang, Nam Khanh and Meyer, Michael and Ahmed, Akram Ben and Abdallah, Abderazek Ben and Tran, Xuan-Tu (2019) 2D-PPC: A single-correction multiple-detection method for Through-Silicon-Via Faults. In: IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 11-14 November 2019, Bangkok.
  4. Xuan-Tuyen Tran, Duy-Anh Nguyen, Duy-Hieu Bui, Xuan-Tu Tran. A Variable Precision Approach for Deep Neural Networks. In Proceedings of the 2019 International Conference on Advanced Technologies for Communications (ATC), 17-19 October 2019, Hanoi.
  5. Pham-Khoi Dong, Hung K. Nguyen, Xuan-Tu Tran. A 45nm High-Throughput and Low Latency AES Encryption for Real-Time Applications. In Proceedings of the 2019 19th International Symposium on Communications and Information Technologies (ISCIT), 25-27 September 2019, Ho Chi Minh city.
  6. Khanh N. Dang, Akram Ben Ahmed, Xuan-Tu Tran. An on-communication multiple-TSV defects detection and localization for real-time 3D-ICs. In Proceedings of the 13rd IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), 1-4 October 2019, Singapore.
  7. Duy Anh Nguyen, Francesca Iacopi, Xuan-Tu Tran. An Efficient Event-driven Neuromorphic Architecture for Deep Spiking Neural Network. In Proceedings of the 32nd IEEE International System-on-Chip Conference (IEEE SOCC), 3-6 September 2019, Singapore.
  8. Duy P. Nguyen, Xuan-Tu Tran, Nguyen L. K. Nguyen, Tan Phat Nguyen, Anh Vu Pham. High Gain High Efficiency Doherty Amplifiers with Optimized Driver Stages. In Proceedings of 2019 62nd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 4-7 August 2019, Dallas, Texas, USA.
  9. Khanh N. Dang, Akram Ben Ahmedy, Abderazek Ben Abdallahz, Xuan-Tu Tran. TSV-IaS: Analytic analysis and low-cost non-preemptive on-line detection and correction method for TSV defects. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 15-17 July 2019, Florida, USA.
  10. Duy P. Nguyen, Xuan-Tu Tran, Nguyen L. K. Nguyen, Phat T. Nguyen, Anh-Vu Pham. A Wideband High Efficiency Ka-Band MMIC Power Amplifier for 5G Wireless Communications. In Proceedings of the 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 26-29 May 2019, Sapporo, Japan. ISBN: 978-1-7281-0397-6.
  11. Duy Anh Nguyen, Huy Hung Ho, Duy-Hieu Bui, Xuan Tu Tran. An Efficient Hardware Implementation of Artificial Neural Network based on Stochastic Computing. In Proceedings of the 5th NAFOSTED Conference on Information and Computer Science (NICS), 23-24 November 2018, Ho Chi Minh city, Vietnam. (In Press)
  12. Kiem Hung Nguyen, Pham Khoi Dong, Xuan Tu Tran. A Reconfigurable Multi-function DMA Controller for High-Performance Computing Systems. In Proceedings of the 5th NAFOSTED Conference on Information and Computer Science (NICS), 23-24 November 2018, Ho Chi Minh city, Vietnam. (In Press)
  13. Manh Hiep Dao, Van Phuc Hoang, Van Lan Dao, Xuan Tu Tran. An Energy Efficient AES Encryption Core for Hardware Security Implementation in IoT Systems. In Proceedings of the 2018 International Conference on Advanced Technologies for Communications (ATC), pp. 301-304, 18-20 October 2018, Ho Chi Minh city, Vietnam. (In Press)
  14. Khanh N. Dang, Xuan-Tu Tran. Parity-based ECC and Mechanism for Detecting and Correcting Soft Errors in On-Chip Communication. In Proceedings of the 12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), pp. 154-161, 12-14 September 2018, Hanoi, Vietnam. ISBN: 978-1-5386-6689-0
  15. Hung K. Nguyen, Xuan-Tu Tran. A Novel Priority-Driven Arbiter for the Router in Reconfigurable Network-on-Chips. In Proceedings of the 2018 International Conference on IC Design & Technology (ICICDT), pp. 25-28, Otranto, 4-6 June 2018. ISBN: 978-1-5386-2550-7
  16. Huy-Hung Ho, Ngoc-Sinh Nguyen, Duy-Hieu Bui, Xuan-Tu Tran. Accurate and Low Complex Cell Histogram Generation by Bypass the Gradient of Pixel Computation. In Proceedings of the 4th NAFOSTED Conference on Information and Computer Science (NICS), pp. 201-206, Hanoi, Vietnam, 24-25 November 2017, ISBN: 978-1-5386-3210-9.
  17. Quang-Linh Nguyen, Dinh-Lam Tran, Duy-Hieu Bui, Duc-Tho Mai, Xuan-Tu Tran. Efficient Binary Arithmetic Encoder for HEVC with Multiple Bypass Bin Processing. In Proceedings of the 7th International Conference on Integrated Circuits, Design, and Verification (ICDV), pp. 82-87, Hanoi, Vietnam, 5-6 October 2017, ISBN: 978-1-5386-3377-9.
  18. Van-Nam Dinh, Hung K. Nguyen, Minh-Trien Pham, Xuan-Tu Tran. An IDPSO Algorithm-based Application Mapping Method for Network-on-Chips. In Proceedings of the 7th International Conference on Integrated Circuits, Design, and Verification (ICDV), pp. 104-110, Hanoi, Vietnam, 5-6 October 2017, ISBN: 978-1-5386-3377-9.
  19. Hai-Phong Phan, Xuan-Tu Tran, Tomohiro Yoneda. Power Consumption Estimation using VNOC2.0 Simulator for a Fuzzy-Logic based Low Power Network-on-Chip. In Proceedings of the 2017 IEEE International Conference on Integrated Circuit Design and Technology, 23-25 May 2017, Texas, USA. [PDF|PrePrint|URL]
  20. Hung K. Nguyen, Xuan-Tu Tran. Design and Implementation of a Hybrid Switching Router for the Reconfigurable Network-on-Chip. In Proceedings of the 2016 International Conference on Advanced Technologies for Communications, 12-14 October 2016, Hanoi, Vietnam.
  21. Hai-Phong Phan, Xuan-Tu Tran. Fuzzy-Logic based Low Power Solution for Network-on-Chip Architectures. In Proceedings of the 2016 International Conference on Advanced Technologies for Communications, 12-14 October 2016, Hanoi, Vietnam.
  22. Duy-Hieu Bui, Diego Puschini, Simone Bacles-Min, Edith Beigne, Xuan-Tu Tran. Ultra Low-Power and Low-Energy 32-bit Datapath AES Architecture for IoT Applications. In Proceedings of the 2016 IEEE International Conference on Integrated Circuit Design and Technology, 27-29 June 2016, Ho Chi Minh city, Vietnam. [PDF|PrePrint|URL]
  23. Thi-Thuy Nguyen, Thanh-Vu Le-Van, Kiem Hung Nguyen, Xuan-Tu Tran. Routing-path Tracking and Updating Mechanism in Reconfigurable Network-on-Chips. In Proceedings of the 2016 IEEE International Conference on Integrated Circuit Design and Technology, 27-29 June 2016, Ho Chi Minh city, Vietnam. [PDF|PrePrint|URL]
  24. Nam-Khanh Dang, Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, Xuan-Tu Tran. Soft-Error Resilient 3D Network-on-Chip Router. The IEEE 7th International Conference on Awareness Science and Technology (IEEE iCAST 2015), 22-24 September 2015, Qinhuangdao, China. [PDF|PrePrint|URL]
  25. Hai-Phong Phan, Xuan-Tu Tran. A Fuzzy-Logic based Voltage-Frequency Controller for Network-on-Chip Routers. In Proceedings of the 11th Conference on PhD Research in Microelectronics and Electronics (IEEE PRIME 2015), Glasgow, Scotland, 29 June - 2 July, 2015. [PDF|PrePrint|URL]
  26. Ngoc-Sinh Nguyen, Duy-Hieu Bui, Xuan-Tu Tran. Reducing Temporal Redundancy in MJPEG using Zipfian Estimation Techniques. In Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems (IEEE APCCAS 2014), pp. 65-68, Okinawa, Japan, November 2014, ISBN: 978-1-4799-5230-4. (Outstanding Student Paper Award & Travel Support Grant Award). [PDF|PrePrint|URL]
  27. Ngoc-Mai Nguyen, Edith Beigne, Suzanne Lesecq, Duy-Hieu Bui, Nam-Khanh Dang, Xuan-Tu Tran. H.264/AVC Hardware Encoders and Low-Power Features. In Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems (IEEE APCCAS 2014), pp. 77-80, Okinawa, Japan, November 2014, ISBN: 978-1-4799-5230-4. [PDF|PrePrint|URL]
  28. Tien-Luan Vu, Van-Quy Quach, Duy-Hieu Bui, Xuan-Tu Tran. A Low-Cost Implementation of Advance Encryption Standard. In Proceedings of the 5th International Conference on Integrated Circuits, Design, and Verification (ICDV 2014), pp. 50-55, Hanoi, November 2014, ISBN: 978-4-88552-294-9. [PDF|PrePrint|URL]
  29. Hung K. Nguyen, Quang-Vinh Tran, Xuan-Tu Tran. Data Locality Exploitation for Coarse-grained Reconfigurable Architecture in Reconfigurable Network-on-Chips. In Proceedings of the 5th International Conference on Integrated Circuits, Design, and Verification (ICDV 2014), pp. 75-81, Hanoi, November 2014, ISBN: 978-4-88552-294-9.[PDF|PrePrint|URL]
  30. Ngoc-Mai Nguyen, Warody Lombardi, Edith Beigné, Suzanne Lesecq, Xuan-Tu Tran. FIFO-level-based Power Management and its Application to a H.264 encoder. In Proceedings of the 40th Annual Conference of IEEE Industrial Electronics Society (IECON 2014), Dallas, TX, USA, October 28 – November 1, 2014. [PDF|PrePrint|URL]
  31. Thi-Thuy Nguyen, Xuan-Tu Tran. A Novel Asynchronous First-In-First-Out Adapting to Multi-synchronous Network-on-Chips. In Proceedings of the 7th International Conference on Advanced Technologies for Communications (ATC 2014), pp. 365-370, Hanoi, Vietnam. ISBN: 978-1-4799-6955-5. [PDF|PrePrint|URL]
  32. Hai-Phong Phan, Xuan-Tu Tran. Thiết kế và mô hình hoá bộ xử lý lô-gic mờ trong điều khiển tần số - điện áp. 2014 National Conference on Electronics, Communications and Information Technology (REV-ECIT2014), Nha Trang, 18-19/9/2014. (in Vietnamese)
  33. Duy-Hieu Bui, Nam-Khanh Dang, Ngoc-Mai Nguyen, Kim-Hung Nguyen, Xuan-Tu Tran. Xây dựng hệ thống mô phỏng và kiểm chứng cho bộ mã hoá tín hiệu video H.264/AVC. 2014 National Conference on Electronics, Communications and Information Technology (REV-ECIT2014), Nha Trang, 18-19/9/2014. (in Vietnamese)
  34. Nam-Khanh Dang, Xuan-Tu Tran, Alain Merigot. An Efficient Hardware Architecture for Inter-Prediction in H.264/AVC Encoders. In Proceedings of the 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (IEEE DDECS 2014), pp. 294-297, April 23-25, 2014, Warsaw, Poland, ISBN: 978-1-4799-4558-0. [PDF|PrePrint|URL]
  35. Thanh-Vu Le-Van, Hai-Phong Phan, Xuan-Tu Tran. High-Level Modeling of a Novel Reconfigurable Network-on-Chip Router. In Proceedings of the first NAFOSTED Conference on Information and Computer Science (NICS 2014), Hanoi, 13-14 March 2014, ISBN: 978-604-67-0228-3. [PDF|URL]
  36. Hai-Phong Phan, Hung K. Nguyen, Duy-Hieu Bui, Nam-Khanh Dang, Xuan-Tu Tran. System-on-Chip Testbed for Validating the Hardware Design of H.264/AVC Encoder. In Proceedings of the 2013 National Conference on Electronics and Communications (REV2013-KC01), Hanoi, December 2013, ISBN: 978-6-04934-664-4. [PDF|URL]
  37. Nam-Khanh Dang, Van-Mien Nguyen, Xuan-Tu Tran. A VLSI Implementation for Inter-Prediction Module in H.264/AVC Encoders. In Proceedings of the 2013 IEICE International Conference on Integrated Circuits, Devices, and Verification (ICDV 2013), pp. 73-78, Ho Chi Minh city, Vietnam, November 2013, ISBN: 978-4-88552-282-6. [PDF|URL]
  38. Ngoc-Sinh Nguyen, Duy-Hieu Bui, Xuan-Tu Tran. An Efficient Video Coding Algorithm Targeting Low Bitrate Stationary Cameras. In Proceedings of the 2013 IEICE International Conference on Integrated Circuits, Devices, and Verification (ICDV 2013), pp. 127-132, Ho Chi Minh city, Vietnam, November 2013, ISBN: 978-4-88552-282-6. [PDF]
  39. Ngoc-Mai Nguyen, Edith Beigne, Suzanne Lesecq, Pascal Vivet, Duy-Hieu Bui, Xuan-Tu Tran. Hardware Implementation for Entropy Coding and Byte Stream Packing Engine in H.264/AVC. In Proceedings of the 2013 International Conference on Advanced Technologies for Communications (ATC 2013), pp. 360-365, October 2013, Ho Chi Minh city, Vietnam, ISBN: 978-1-4799-1086-1. [PDF|PrePrint|URL]
  40. Tung Nguyen, Duy-Hieu Bui, Hai-Phong Phan, Trong-Trinh Dang, Xuan-Tu Tran. High-Performance Adaption of ARM Processor into Network-on-Chip Architectures. In Proceedings of the 26th IEEE System-on-Chip Conference (IEEE SOCC 2013), pp. 222-227, September 2013, Erlangen, Germany. [URL|DOI]
  41. Thi-Thuy Nguyen, Xuan-Tu Tran. A Synchronous-to-Synchronous FIFO Architecture for Multi-synchronous Network-on-Chips. International Conference on Green and Human Information Technology (ICGHIT 2013), pp. 111-117, Hanoi, Vietnam, February 27 – March 1, 2013.
  42. Viet-Thang Nguyen, Xuan-Tu Tran, Ha Vu Le . An Efficient Algorithm of Inter-Prediction Coding for H.264/AVC Encoders. International Conference on Green and Human Information Technology (ICGHIT 2013), Hanoi, Vietnam, February 27 – March 1, 2013.
  43. Tran Van Hoang, Nguyen Ly Thien Truong, Hoang Trang, Xuan-Tu Tran. Design and Implementation of a SoPC System for Speech Recognition. International Conference on Green and Human Information Technology (ICGHIT 2013), Hanoi, Vietnam, February 27 – March 1, 2013, ISSN: 1876-1100 (Scopus Journal).
  44. Ngoc-Mai Nguyen, Xuan-Tu Tran, Pascal Vivet, Suzanne Lesecq. An Efficient Context Adaptive Variable Length Coding Architecture for H.264/AVC Video Encoders. In Proceedings of the 5th International Conference on Advanced Technologies for Communications (ATC 2012), pp. 158-164, Hanoi, October 2012, ISBN: 978-1-4673-4350-3. [PDF|PrePrint|URL] (Best Student Paper Award)
  45. Thanh-Vu Le-Van, Xuan-Tu Tran. Simulation and Performance Evaluation of a Network-on-Chip Architecture based on SystemC. In Proceedings of the 5th International Conference on Advanced Technologies for Communications (ATC 2012), pp. 170-175, Hanoi, October 2012, ISBN: 978-1-4673-4350-3.
  46. Thanh-Vu Le-Van, Dien-Tap Ngo, Xuan-Tu Tran. A SystemC based Simulation Platform for Network-on-Chip Architectures. In Proceedings of the 2012 IEICE International Conference on Integrated Circuits and Devices in Vietnam (ICDV 2012), pp. 132-136, Danang, August 2012, ISBN: 978-4-88552-264-2.
  47. Duy-Hieu Bui, Van-Huan Tran, Van-Mien Nguyen, Duc-Hoang Ngo, Xuan-Tu Tran. A Hardware Architecture for Intra Prediction in H.264/AVC Encoder. In Proceedings of the 2012 IEICE International Conference on Integrated Circuits and Devices in Vietnam (ICDV 2012), pp. 95-100, Danang, August 2012, ISBN: 978-4-88552-264-2.
  48. Nam-Khanh Dang, Thanh-Vu Le-Van, Xuan-Tu Tran. FPGA Implementation of a Low Latency and High Throughput Network-on-Chip Router Architecture. In Proceedings of the 2011 International Conference on Integrated Circuits and Devices in Vietnam (ICDV 2011), Hanoi, August 2011.
  49. Duy-Hieu Bui, Xuan-Tu Tran. Multi-level Design Methodology using SystemC and VHDL for JPEG Encoder. In Proceedings of the 2011 International Conference on Integrated Circuits and Devices in Vietnam (IEICE ICDV 2011), Hanoi, August 2011.
  50. Xuan-Tu Tran, Van-Huan Tran. Cost-Efficient 130nm TSMC Forward Transform and Quantization for H.264/AVC Encoders. In Proceedings of the IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (IEEE DDECS 2011), pp. 47-52, Cottbus, Germany, April 2011.
  51. Van-Huan Tran, Xuan-Tu Tran. An Efficient Architecture Design for VGA Monitor Controller. In Proceedings of the International Conference on Consumer Electronics, Communications and Networks (IEEE CECNet 2011), pp. 3917-3921, Hubei, China, April 2011, ISBN: 978-1-61284-459-6.
  52. Van-Huan Tran, Ngoc-Mai Nguyen, Van-Mien Nguyen, and Xuan-Tu Tran. Low Cost and High Performance Implementation of Forward Transform and Quantization for an H.264/AVC Encoder. In Proceedings of the Solid-State Systems Symposium (4S), pp. 231-236, Ho Chi Minh city, Vietnam, June 2010. [URL|DOI]
  53. Xuan-Tu Tran, Hai-Phong Phan, Van-Huan Tran, Quang-Vinh Tran, and Ngoc-Binh Nguyen. Design and Implementation of an AMBA AHB Compliant Bus Architecture on FPGA. In Proceedings of the IEICE VLSI Design Technologies (VLD 2010) conference, pp. 169-174, Okinawa, Japan, March 2010, ISSN: 0913-5685. [PDF|URL|DOI]
  54. Yvain Thonnart, Xuan-Tu Tran, Pascal Vivet, Edith Beigné, Fabien Clermidy, Jean Durupt. An Asynchronous Low-Power Innovative Network-on-Chip including Design-for-Test capabilities. In Proceedings of the 2009 International Conference on Advanced Technologies for Communications (ATC 2009), pp. 59–62, Hai Phong, Vietnam, October 2009. (Invited paper) [PDF|URL|DOI]
  55. P.T. Hong, Phi-Hung Pham, Xuan-Tu Tran, Chulwoo Kim. Analysis and evaluation of traffic-performance in a backtracked routing network-on-chip. In Proceedings of the 2nd International Conference on Communications and Electronics (ICCE 2008), pp. 13–17, Hoi An, Vietnam, June 2008. [PDF|URL|DOI
  56. E. Beigne, F. Clermidy, J. Durupt, H. Lhermet, S. Miermont, Y. Thonnart, T. Tran-Xuan, A. Valentian, D. Varreau, P. Vivet. An Asynchronous Power Aware and Adaptive NoC Based Circuit. In Proceedings of the 2008 Symposium on VLSI Technology and Circuits, Hilton Hawaiian Village, Honolulu, Hawaii, June 2008. [PDF|URL|DOI] - citations
  57. Xuan-Tu Tran, Yvain Thonnart, Jean Durupt, Vincent Beroulle, and Chantal Robach. A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application. In Proceedings of the ACM/IEEE International Symposium on Networks-on-Chips (NOCS 2008), pp. 149–158, Newcastle upon Tyne, UK, April 2008. [PDF|URL|DOI] (Student Travel Grant Award- citations
  58. Xuan-Tu Tran, Yvain Thonnart, Jean Durupt, F. Bertrand, Vincent Beroulle, and Chantal Robach. Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip. In Proceedings of the ACM/IEEE International Symposium on Net-works-on-Chips (NOCS 2007), pp. 216–216, New Jersey, USA, May 2007. [PDF|URL|DOI] - citations
  59. Xuan-Tu Tran, Jean Durupt, F. Bertrand, Vincent Beroulle, and Chantal Robach. How to Implement an Asynchronous Test Wrapper for Networks-on-Chip Nodes. In Informal Proceedings of the 12th IEEE European Test Symposium (ETS 2007), pp. 29–34, Freiburg, Germany, May 2007. [PDF|URL|DOI] - citations
  60. Xuan-Tu Tran, Jean Durupt, F. Bertrand, Vincent Beroulle, and Chantal Robach. A DFT Architecture for Asynchronous Networks-on-Chip. In Proceedings of the IEEE European Test Symposium (ETS 2006), pp. 219–224, Southampton, UK, May 2006. [PDF|URL|DOI] - citations
  61. Xuan-Tu Tran, Vincent Beroulle, Jean Durupt, Chantal Robach, and F. Bertrand. Design-for-Test of Asynchronous Networks-on-Chip. In Proceedings of the IEEE Work-shop on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2006), pp. 163–167, Prague, Czech, April 2006.
  62. Xuan-Tu Tran, Jean Durupt, F. Bertrand, Vincent Beroulle, and Chantal Robach. Conception en Vue de Test pour l’Architecture d’un Réseau sur Puce Asynchrone. In Proceedings of Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM 2006), pp. 504–507, Rennes, France, May 2006.
  63. Dien-Tap Ngo and Xuan-Tu Tran. Control over the Power Lines. In Proceedings of the Asian International Conference on Power System Protection, pp. 578–581, Nanjing, China, October 2003.
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